This invention relates to a memory system for a computer. It relates particularly to a word organized, random access, read-write or read-only memory of the kind having a semiconductor array with a data field and a data check field for detecting data errors in each word. The invention is applicable also to memory arrays other than semiconductor arrays, for example, core memory and other types of bit storage means. The memory word may represent more than one data word in a particular computer.
The present invention is applicable to a memory system of the kind in which a processor module is associated with one or more memory modules.
The memory system of the present invention permits data errors, addressing errors and operation errors to be detected.
Errors in stored data can be caused by the sticking of one or more bits in a data word stored in a semiconductor memory, and such errors can be detected by associating a data check field with the data field of the stored word. Various types of errors can be detected by codes associated with the data check fields. For example, with a Hamming code like that disclosed in U.S. Pat. No. 4,228,496 issued Oct. 14, 1980, (and assigned to the same assignee as the assignee of the present application) all single bit data errors can be detected and corrected, all double bit data errors can be detected and some errors involving more than two data bits can be detected.
To increase the overall reliability of a memory system, it is desirable to detect addressing errors as well as errors in the stored data.
It is known to build a self-checking memory address decoder in the straightforward way (by duplicating and comparing outputs; but this can become prohibitive in size and cost as the size of the address increases. Thus, in a 20 bit address there are two to the twentieth power decoder outputs, requiring roughly two to the eighteenth power (about 262,000) integrated circuits just to compare. In addition, in a real main memory the address decoding is carried out at several levels: first a "module compare" to select one of several PC boards, then a "row decode" to select one word of memory devices, then internal X-Y decoders to select an individual bit cell in the memory devices. This creates further problems in obtaining a self-checking operation of memory address.
Obtaining satisfactory address error detection with a reasonable integrated circuit package count has been a problem in the prior art.
Data error detection and/or correction itself does not protect against an operation error in a memory system. For example, if contention on a bus should result in producing a write command at the wrong time, the error system for detecting stuck bits in a data field would not give any protection against the memory error resulting from the erroneous operation command.
To provide high reliability in a memory system, it is desirable to insure that the operations of each memory module are in step with the operations of the associated processor module.
It is a primary object of the present invention to detect address errors by coding address parity information into the data check field of each memory location.
It is a related object to detect address errors by an encoding technique that does not require storing the address for address error detection.
It is another related object to increase the system-level reliability by a substantial amount, as much as 10 to 100 times, by including the address parity bit method in an already existing data check code generation system so that address error detection can be obtained at essentially no cost.
It is a further object of the present invention to insure that all memory modules and the memory control in the processor are receiving the same commands.
It is a related object to detect any difference in the operations sequence between the processor and all memory modules and to provide an interrupt to the processor if there is a difference.
It is a related object to generate a signal in each memory module indicating the status of operation of that memory module and to transmit that signal to operation check logic in the processor for comparison to the status of operations of the processor module.
It is a still further object of the present invention to combine data error, address error and operation error detection in a memory system to increase the system level reliability.